Programmable integrated circuits (ICs) are often used to implement digital logic operations according to user configurable input. Example programmable ICs include complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). CPLDs often include several function blocks that are based on a programmable logic array (PLA) architecture with sum-of-products logic. A configurable interconnect matrix transmits signals between the function blocks.
One type of FPGA includes an array of programmable tiles. The programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect Express (PCIe) and Ethernet and so forth. Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
A conventional design process for programmable ICs begins with the creation of the design. The design is then compiled for implementation in a particular programmable IC device. The design can include user designed circuits, as well as one or more pre-designed circuit modules, sometimes referred to as “Intellectual Property (IP) cores.” Such IP cores can be parameterized and added to a design before the design is implemented for a programmable IC device. Some IP cores, however, require information about resource-mapping prior to implementation of the design (e.g., at design-time). Assigning resources, such as input/output (IO) resources, to IP cores at design-time can lead to resource contention and conflict, particularly if the design includes multiple IP cores. Further, if a design wishes to alter resource assignments, the designer must return to the design stage, re-assign resources to the IO core(s), and repeat the implementation process.